1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to semiconductor memory devices which include floating body capacitorless memory cells and to methods of operating such devices.
A claim of priority is made to Korean Patent Application No. P2005-0118907, filed Dec. 7, 2006, the entirety of which is incorporated herein by reference.
2. Description of the Related Art
Typically, the memory cells of dynamic random access memory (DRAM) devices are composed of a capacitor for storing charges and a transistor for accessing the capacitor. A logic value of each memory cell is determined by a voltage of the capacitor. However, in an effort to increase device integration, DRAM memory cells composed of a single transistor have been proposed. These single-transistor type memory cells are referred to herein as “floating body transistor capacitorless memory cells”, and in some instances, the short-hand phrase “transistor cell” is utilized.
In a write mode, the threshold voltage of a floating body transistor capacitorless memory cell is varied by altering the channel body potential of the cell, and in a read mode, logic states are discriminated based on an amount of current passing through the cell. This is explained in more detail below with reference to FIG. 1.
FIG. 1 is a cross-sectional schematic view of an example of a floating body transistor capacitorless memory cell. As shown, the floating body transistor capacitorless memory cell of this example includes a silicon (Si) substrate 100 and a buried oxide layer 101. Located over the buried oxide layer 101 is a floating channel body region 102 interposed between source and drain regions 103 and 104. A gate dielectric 105 and gate electrode 106 are aligned over a floating channel body region 102, and insulating layers 107 (e.g., SiO2 layers) are formed to isolate the floating body transistor capacitorless memory cell from other devices on the substrate 100.
Logic “1” and “0” states are dependent upon the threshold voltage Vth of the floating body transistor capacitorless memory cell, and examples of write and read voltages applied to the floating body transistor capacitorless memory cell are illustrated below in Table 1:
TABLE 1Threshold (Vth)Source (Vs)Gate (Vg)Drain (Vd)Write “1”Low0 V1.5 V1.5 VWrite “0”High0 V1.5 V−1.5 V  Readn/a0 V1.5 V0.2 V
In a write data “1” operation, a voltage bias condition is set in which Vgs>Vth and Vgd<Vth. This causes the transistor cell to operate in a saturation region. In this state, impact ionization occurs at the junction between the drain region 104 and the floating channel body region 102. As a result, holes are injected in the floating channel body region 102. This increases the potential of the floating channel body region 102 and reduces the threshold voltage Vth of the floating body transistor capacitorless memory cell.
In a write data “0” operation, the drain voltage Vd is dropped to a negative voltage to create a forward bias condition at the junction between the floating channel body region 102 and the drain region 104. The forward bias causes holes contained in the floating channel body region 102 to migrate into the drain region 104. This reduces the potential of the floating channel body region 102 and increases the threshold voltage Vth.
In a read operation, a voltage bias condition is set such that Vgs>Vth and Vgd>Vth, and such that the transistor cell is operated in its linear region. A drain current is measured and compared to a reference cell current to thereby distinguish whether the floating body transistor capacitorless memory cell is in a high (logic “0”) or low (logic “1”) voltage threshold Vth state. More particularly, if the measured drain current is less than the reference current, then a logic “0” state is read. If the measured drain current is more than the reference current, then a logic “1” state is read.
Conventionally, the reference cell current is generated using reference (or dummy) transistor cells which are respectively programmed to “0” and “1” states. In addition, a reference voltage generating circuit and other circuits are utilized to generate a reference current which lies between the drain currents of the “0” and “1” reference transistor cells. See, for example, U.S. Pat. No. 6,567,330, issued May 20, 2003, in the name of Fujita et al.
The reading of floating body transistor capacitorless memory cells is prone to a variety of errors. Examples of such errors are described next with reference to FIGS. 2A through 2C.
FIGS. 2A and 2B shows “0” state and “1” state drain current distributions 201 and 202 of a number of floating body transistor capacitorless memory cells, and reference cell current distributions 203 associated with multiple read operations. FIG. 2A illustrates the case where the reference cell current distribution 203 and the “0” state drain current distribution 201 overlap at 210, and FIG. 2B illustrates the case where the reference cell current distribution 203 and the “1” state drain current distribution 202 overlap at 211. In either case, read errors will occur. The overlap conditions 210 and 211 of FIGS. 2A and 2B can result from a number of factors, including process variations, temperature variations, and so on.
FIG. 2C shows the case where the transistor cell “0” state and “1” state drain current distributions 201 and 202 overlap one another at 212. This can result from the volatile nature of floating body transistor capacitorless memory cells. That is, leakage from the floating channel body region can cause the threshold voltages Vth of the cell transistors to drift. It is therefore necessary to periodically refresh floating body transistor capacitorless memory cells much in the same way that conventional capacitor-type DRAM cells are refreshed.
In addition to the propensity for reading errors described above, the conventional floating body transistor capacitor-less memory cell DRAM device suffers the drawback of requiring the provision of a reference current generator, reference memory cells and other circuits to generate the reference current. These can prove burdensome when attempting to increase the density of the memory device. Also, additional time is consumed in a refresh operation to refresh the reference memory cells.